Gate and CMOS structure and MOS structure

ABSTRACT

Provided are a novel gate, a CMOS structure, and a MOS structure each of that has low resistance and excellent controllability. The gate is comprised of an intermetallic compound semiconductor that has an electric conductivity in a range of no less than 10 2  S·m −1 , nor more than 10 5  S·m −1  without impurities and has a band structure like that of a semiconductor.

FIELD OF THE INVENTION

The invention of this application relates to a gate, CMOS structure, andMOS structure. More particularly, the invention of this applicationconcerns a novel gate that replaces a conventional gate and that isuseful for a next-generation integrated circuit, and a novel CMOSstructure and MOS structure each of that uses that gate.

DESCRIPTION OF THE RELATED ART

The requirements that are demanded regarding the next-generationintegrated circuits are (1) the increase in the integrated level, (2)the increase in the speed, and (3) the decrease in the powerconsumption. As a structure that satisfies these requirements, aComplementary Metal Oxide Semiconductor (CMOS) structure is known.

For example, as illustrated in FIG. 3, a field effect transistor (FET)of a conventional CMOS structure uses a silicon oxide film of SiO₂ as agate insulative film (2) and has its gate constructed of a gate (1) thatuses polycrystalline silicon (polysilicon) made to contain an n-typeimpurity therein.

Ordinarily, the threshold value voltage Vth that is a voltage thatallows a bias voltage to be applied to the gate (1) to thereby startcausing the flow of a channel-opening current is determined dependingbasically upon the Fermi level of a substrate Si and that of the gatematerial. For this reason, in the CMOS structure, the threshold voltageVth differs between the n-type substrate and a p-type substrate.

On this account, because for making the CMOS operation stable it isnecessary to make the both threshold voltages Vth substantially the samein level, the Vth is conventionally controlled by performingion-implantation of impurities into either channel region.

In this case, as illustrated, one channel is a surface channel and theother one is a buried channel. And, in case of the polycrystalline Sithat is a semiconductor, the position of the Fermi level can becontrolled over a wide range by changing the impurity concentrationtherein and, accordingly, the Vth can be freely set and controlled alsowith respect to the electric conductivity (p, n) of the substrate.

However, the conventional CMOS structure as described above has thefollowing problems when trying to further increase the integratedversion level of the integrated circuit.

Namely, the demand for the micronizing of the gate wire width that isimportant for high integration has more and more increased, andtherefore it is necessary to prevent the increase in the resistancefollowing such micronization. However, as described above, in the caseof the polycrystalline Si gate (1) made by doping the polycrystalline Siwith impurities, a limit has started to be imposed upon the suppressionof the resistance.

In order to solve this problem, constructing the gate (1) using metalhas been proposed, and as a result, the using of a high-melting pointmetal such as tungsten has nowadays been studied and examined. However,in case of a metal gate, it is pointed out that the following problemscome up. Namely, (a) because the Vth is determined in accordance withthe work function of the Fermi level of the backing Si and the metal,the range of control of the Fermi level that had theretofore been freelyset becomes narrow, with the result that the problem that the Vthbecomes difficult to control arises. (b) The adherences between themetal and gate insulative films such as SiO₂ are bad. (c) Owing to thediffusion of the metal there increases the leak current of the gateinsulative film. (d) The metal becomes diffused up to the channelregion, whereby trap of the carriers occurs. And so forth.

Also, recently, the metal silicide (3) which is an intermetalliccompound having an electric conductivity substantially the same as thatof metal has been found out as being usable. Thereby, providing it onthe polycrystalline Si gate (1) as illustrated in FIG. 4 has beenproposed with an aim to decrease the gate resistance even to a smallextent. However, even in this case, although the above-describedproblems such as those following the use of metal do not exist, becausethe metal silicide (3) is merely provided on the gate (1), it doesn'thappen that the resistance of the gate (1) itself will decrease.Therefore, realizing the remarkable decrease in the resistance is notexpected.

The invention of this application has been made in view of the existingcircumstances mentioned above and has an object to provide a novel gatethat can solve the points in problem inherent in the prior art, that canrealize the decrease in resistance to such an extent as not in the priorart, and that can greatly contribute to further increasing theintegrated version level of the integrated circuit, and a novel CMOSstructure and MOS structure each of that uses such gate.

DISCLOSURE OF INVENTION

To attain the above object, the invention of this application provides agate (first aspect) comprising an intermetallic compound semiconductorthat has an electric conductivity in a range of no less than 10² S·m⁻¹,nor more than 10⁵ S·m⁻¹ without impurities and that has a semiconductorband structure. Also, the invention of this application provides a gate(second aspect) wherein, impurities are added to the said intermetalliccompound semiconductor.

Also, the invention of this application also provides a gate wherein, inthe above-described gate, the intermetallic compound semiconductor is acompound of a metal and a IV-group element (third aspect) or wherein, inthe above-described gate, any of C, Si, and Ge is used as the IV-groupelement (fourth aspect.)

The invention of this application also provides a gate wherein, in theabove-described gate, (fifth aspect), any one intermetallic compoundsemiconductor of CrSi₂, MnSi₂, MoSi₂, Ru₂Si₃, WSi₂, ReSi_(1.75-2), OsSi,OS₂Si₃, OsSi₂, FeSi₂, IrSi₂, BaSi₂, CaSi₂ and Mg₂Si is used.

Further, the invention of this invention also provides a CMOS structurethat uses the above-described gate (sixth aspect), or a MOS structurethat uses the above-described gate (seventh aspect).

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a view illustrating a CMOS structure that uses a gateaccording to an embodiment of the invention of this application;

FIG. 2 is a graph of relation between wavelength—spectral intensity ofIrSi₂ according to an embodiment of the invention of this application;

FIG. 3 is a view illustrating a conventional CMOS structure; and

FIG. 4 is a view illustrating another conventional CMOS structure.

Here, reference numerals in the drawings designate as follows:

-   1. Gate-   2. Gate insulative film-   3. Metal silicide-   4. Gate for use for n type-   5. Gate for use for p type

BEST MODES FOR CARRYING OUT THE INVENTION

The invention of this application has been achieved based on thecompletely new knowledge procured by the inventors of the invention ofthis application that as the material for the gate there is used an anintermetallic compound semiconductor, i.e. one having an electricconductivity in a range of no less than 10² S·m⁻¹, nor more than 10⁵S·m⁻¹ without impurities and also having a semiconductor band structure.As a result of this, the invention of this application can be a basictechnique that enables realizing further decrease in the resistance andthat therefore is indispensable to the integrated circuit of the nextgeneration and the next, but that next, generation.

More specifically, this intermetallic compound semiconductor (1) has anelectric conductivity in a range of no less than 10² S·m⁻¹, nor morethan 10⁵ S·m⁻¹ without impurities. (2) has a semiconductor bandstructure, and (3) is a semiconductor compound that is comprised ofmetal and a semiconductor.

First, (1) that the intermetallic compound semiconductor has an electricconductivity in a range of no less than 10² S·m⁻¹, nor more than 10⁵S·m¹ without impurities. The electric conductivity of a semiconductor ingeneral is in a range of from 10⁻² to 10⁴ S·m⁻¹ at normal temperature,whereas an electric conductivity of metal in general is in a range offrom 10⁶ to 10⁸ S·m⁻¹ at normal temperature. An intermetallic compoundsemiconductor, which is used for a gate material of the invention ofthis application, has a electric conductivity closed to an electricconductivity of metal compare to a semiconductor in general. Also, theelectric conductivity of the intermetallic compound semiconductor can beimproved by adding impurities.

Next, (2) the wording “a semiconductor band structure” means that theintermetallic compound semiconductor has an electric-conductionmechanism that enables freely controlling the Fermi level. As a resultof this, it becomes possible to control the threshold voltage Vth,whereby it becomes possible to realize a gate for use for n type on then-type substrate and a gate for use for p type on the p-type substrate.Namely, owing to this property, the intermetallic compound semiconductorbecomes able to be used as the material for use for gate.

(3) Regarding the semiconductor compound of metal and a semiconductorthat can be the material having the above-described two properties, forexample, there is a compound of metal and an element of the IV-group.More specifically, there can be taken up as examples thereof thecompounds of metals and silicon such a CrSi₂, MnSi₂, MoSi₂, Ru₂Si₃,WSi₂, ReSi_(1.75-2), OsSi, Os₂Si₃, OsSi₂, FeSi₂, IrSi₂, BaSi₂, CaSi₂,Mg₂Sior the compounds the compositions of that each are in theneighborhood of that of those compounds. The compounds in this case canbe called “semiconductor silicides”. In addition, there can be alsotaken up as such examples compounds of metal and C or Ge. Furthermore,compounds of metal and Si and C or Ge can also be said material. And,for example, in the case of FeSi₂, pn control becomes possible by dopingCo and Cr.

The gate according to the invention of this application that consists ofthe intermetallic compound semiconductor having the above-describedproperties not only has excellent low resistance but also enablesrealizing easy control. The freedom in which the CMOS structure can bedesigned is thereby greatly widened. Also, since both of the np channelsbecome surface channels, it is also possible to avoid having theshort-channel effect. Furthermore, the ion-implantation of impuritiesthat needed to be so far performed becomes unnecessary, whereby theproperty of the channel region being crystalline can also be ensured.

And, through the use of this gate, it is possible to realize the CMOSstructure that is simple and that has excellent controllability ofprocess. Of course, the gate according to the invention of thisapplication can needless to say be applied also to the MOS structure.Excellent effects that are as in the case of the CMOS structure arerealized.

While the invention of this application has the characterizing featuresas described above, an example thereof will hereafter be described alongthe drawings annexed hereto to thereby give a more detailed explanationof the mode of this invention.

EXAMPLE

FIG. 1 illustrates a CMOS structure that uses a gate according to anembodiment of the invention of this application. And any oneintermetallic compound semiconductor of CrSi₂, MnSi₂, MoSi₂, Ru₂Si₃,WSi₂, ReSi_(1.75-2), OsSi, Os₂Si₃, OsSi₂, FeSi₂, IrSi₂, BaSi₂, CaSi₂ andMg₂Si is used for the gate material. In this CMOS structure, bycontrolling a pn conduction mechanism of the intermetallic compoundsemiconductor, a gate (10) for use for n type is provided on an n-typesubstrate and a gate (11) for use for p-type is provided on a p-typesubstrate.

In this case, as stated previously, it is not only possible to make theresistance lower but do the both channels also become surface channels.Therefore, the illustrated CMOS structure does not have theshort-channel effect which conventionally occurred in the buried channelin the CMOS structure. Resultantly, the illustrated CMOS structureprovides a gate and CMOS structure that are again better for conversioninto an integrated version.

Also, FIG. 2 shows a graph of light absorption spectrum of IrSi₂ as anembodiment of above-described intermetallic compound semiconductor. Thevertical axis in FIG. 2 shows spectral intensity and the horizontal axisin FIG. 2 shows wavelength.

As FIG. 2 shows, the band gap of IrSi₂ is 1.13 eV because of there isspectral absorption around 1100 nm wavelength. That is, it shows thatthe IrSi₂has a semiconductor band structure.

Of course, the invention is not limited to the above-described examplebut permits various aspects to be made regarding finer portions of theinvention.

INDUSTRIAL APPLICABILITY

As has been explained above in detail, by the invention of thisapplication, there is realized a novel gate for the next generation thathas excellent low resistance characteristics and excellentcontrollability, and there are also provided a novel CMOS structure andMOS structure each of that uses that gate to thereby enable a furtherdevelopment of the integrated circuit.

1. A CMOS structure comprising a gate comprising an intermetalliccompound semiconductor selected from the group consisting of MnSi₂,Ru₂Si₃, Os₂Si₃, OsSi₂, BaSi₂, and Mg₂Si, wherein the intermetalliccompound semiconductor is without impurities, has an electricconductivity in a range of no less than 10² S·m⁻¹, nor more than 10⁵S·m⁻¹, and has a semiconductor band structure.
 2. A MOS structurecomprising a gate comprising an intermetallic compound semiconductorselected from the group consisting of MnSi₂, Ru₂Si₃, Os₂Si₃, OsSi₂,BaSi₂, and Mg₂Si, wherein the intermetallic compound semiconductor iswithout impurities, has an electric conductivity in a range of no lessthan 10² S·m⁻¹, nor more than 10⁵ S·m⁻¹, and has a semiconductor bandstructure.